Semiconductor memory device having thin film transistor and method of producing the same

ABSTRACT

A semiconductor memory device includes a semiconductor substrate, and a memory cell formed on the semiconductor substrate and including two transfer transistors, two driver transistors and two thin film transistor loads. The thin film transistor load includes a first gate electrode, a first insulator layer formed on the first gate electrode, a semiconductor layer formed on the first insulator layer, a second insulator layer formed on the semiconductor layer, and a shield electrode formed on the second insulator layer. This shield electrode shields the thin film transistor.

This application is a continuation, of application Ser. No. 07/857,643,filed Mar. 24, 1992, now abandoned.

BACKGROUND OF THE INVENTION

The present invention generally relates to semiconductor memory devicesand methods of producing the same, and more particularly to a thin filmtransistor (TFT) load type static random access memory (SRAM) and amethod of producing such a TFT load type SRAM.

Up to now, the high resistance load type SRAM was popularly used.However, as the integration density improves and the number of memorycells increases, the current consumption increases and various problemsare generated. In order to avoid such problems and the help of theprogress in the semiconductor technology, the SRAM having the TFT loadhas been realized. However, new problems are generated due to the use ofthe TFT load, and it is necessary to eliminate these new problems.

An example of a conventional method of producing the high resistanceload type SRAM will be described with reference to FIGS. 1A through 1Jand FIGS. 2A through 2F. FIGS. 1A through 1J are side views in crosssection showing essential parts of the high resistance load type SRAM atessential stages of the conventional method of producing the highresistance load type SRAM. FIGS. 2A through 2F are plan views of thehigh resistance load type SHAM at essential stages of the conventionalmethod of producing the high resistance load type SRAM. FIGS. 1A through1J respectively are cross sections taken along a line which correspondsto a line Y--Y in the plan view of FIG. 2F.

In FIG. 1A, a silicon dioxide (SiO₂) layer is used as a pad layer, forexample, and a silicon nitride (Si₃ N₄) layer which is formed on theSiO₂ layer is used as an oxidation resistant mask layer when carryingout a selective thermal oxidation (for example, a local oxidation ofsilicon (LOCOS)) so as to form a field insulator layer 2 on a silicon(Si) semiconductor substrate 1. This field insulator layer 2 is made ofSiO₂ and has a thickness of 4000 Å, for example.

Then, the Si₃ N₄ layer and the SiO₂ layer which are used when carryingout the selective thermal oxidation are removed to expose an activeregion of the Si semiconductor substrate 1.

In FIG. 1B, a thermal oxidation is carried out to form a gate insulatorlayer 3 which is made of SiO₂ and has a thickness of 100 Å, for example.

By carrying out a resist process of the photolithography technique and awet etching using hydrofluoric acid as the etchant, the gate insulatorlayer 3 is selectively etched to form a contact hole 3A.

In FIGS. 1C and 2A, a chemical vapor deposition (CVD) is carried out toform a first polysilicon layer having a thickness of 1500 Å, forexample.

Then, a vapor phase diffusion is carried out to introduce phosphorus (P)of 1×10²⁰ cm⁻³, for example, so as to form an n⁺ -type impurity region5'.

In FIG. 2A, the illustration of the first polysilicon layer is omittedfor the sake of convenience.

In FIG. 1D, a resist process of the photolithography technique and areactive ion etching (RIE) using CCl₄ /O₂ as the etching gas are carriedout to pattern the first polysilicon layer and form a gate electrode 4.The gate electrode 4 becomes the gate electrode of a word line and adriver transistor.

An ion implantation is carried out to inject As ions with a dosage of3×10¹⁵ cm⁻² and an acceleration energy of 40 keV, so as to form a sourceregion 5 and a drain region 6.

In FIGS. 1E and 2B, a CVD is carried out to form an insulator layer 7which is made of SiO₂ and has a thickness of 1000 Å, for example.

By carrying out a resist process of the photolithography technique and aRIE using CHF₃ /He as the etching gas, a ground line contact hole 7A isformed. This ground line contact hole 7A cannot be seen in FIG. 1E.

In FIG. 1F, a CVD is carried out to form a second polysilicon layerhaving a thickness of 1500 Å, for example.

Then, an ion implantation is carried out to inject P ions into thesecond polysilicon layer with a dosage of 4×10¹⁵ cm⁻² and anacceleration energy of 30 keV, and an annealing is carried out to reducethe resistance.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the second polysiliconlayer and form a ground line 8.

In FIGS. 1G and 2C, a CVD is carried out to form an insulator layer 9which is made of SiO₂ and has a thickness of 1000 Å, for example.

A resist process of the photolithography technique and a RIE using CHF₃/He as the etching gas are carried out to selectively etch the insulatorlayers 9 and 7 and form a load resistor contact hole 9A.

In FIG. 1H, a CVD is carried out to form a third polysilicon layerhaving a thickness of 1500 Å, for example.

A resist process of the photolithography technique and an ionimplantation with a dosage of 1×10¹⁵ cm⁻² and an acceleration energy of30 keV are carried out to inject As ions into a part where a supply lineof a positive power source voltage Vcc is formed and a part where thehigh resistance load makes contact with the gate electrode 4.

By carrying out a resist process of the photolithography technique and aRIE using CCl₄ /O₂ as the etching gas, the third polysilicon layer ispatterned to form a contact part 10, a high resistance load 11 and a Vccsupply line 12.

In FIGS. 1I and 2D, a CVD is carried out to form an insulator layerwhich is made of SiO₂ and has a thickness of 1000 Å, for example, and aninsulator layer which is made of phosphosilicate glass (PSG) and has athickness of 5000 Å, for example. In FIG. 1I, these insulator layers arereferred to as an insulator layer 13.

A thermal process is thereafter carried out to reflow and planarize theinsulator layer 13.

Next, a resist process of the photolithography technique and a RIE usingCHF₃ /He as the etching gas are carried out to selectively etch theinsulator layer 13 and the like and to form a bit line contact hole 13A.

In FIGS. 1J and 2E, a sputtering is carried out to form an aluminum (Al)layer having a thickness of 1 μm, for example. This Al layer ispatterned using the normal photolithography technique so as to form abit line 14. Those elements which are shown in FIGS. 1J and 2E but notyet described such as "BL" will be readily understood from thedescription given later in conjunction with FIG. 3.

FIG. 2F shows the plan view of the essential part of the high resistanceload type SRAM which is completed by the above described processes. InFIG. 2F, those parts which are the same as those corresponding parts inFIGS. 1A through 1J and FIGS. 2A through 2E are designated by the samereference numerals. However, for the sake of convenience, theillustration of the Al bit line 14 shown in FIGS. 1J and 2E is omittedin FIG. 2F.

FIG. 3 shows an equivalent circuit diagram of the essential part of thehigh resistance load type SRAM described above in conjunction with FIGS.1A through 1J and 2A through 2F.

FIG. 3 shows driver transistors Q1 and Q2, transfer gate transistors Q3and Q4, high resistance loads R1 and R2, a word line WL, bit lines BLand/BL, nodes S1 and S2, the positive power source voltage Vcc, and anegative power source voltage Vss.

The operation of this high resistance load type SRAM, the storageoperation in particular, is carried out as follows.

If it is assumed that the positive power source voltage Vcc is 5 V, thenegative power source voltage Vss is 0 V, the node S1 is 5 V and thenode S2 is 0 V, the transistor Q2 is ON and the transistor Q1 is OFF.The potential at the node S1 is maintained to 5 V if the transistor Q1is OFF and the resistance is sufficiently high compared to the highresistance load R1. The potential at the node S2 is maintained to 0 V ifthe transistor Q2 is ON and the resistance is sufficiently low comparedto the high resistance load R2.

However, under the above described condition, a D.C. current flows fromthe positive power source voltage Vcc supply line to the negative powersource voltage Vss supply line via the node S2, and the current value isinversely proportional to the value of the high resistance load R2.

When the integration density of the above described high resistance loadtype SRAM increases, the number of memory cells per chip increases andthe current consumption of the entire chip would become very large ifthe current consumption per memory is not reduced. Hence, the D.C.current described above must be reduced, but in order to reduce thisD.C. current, the values of the high resistance loads R1 and R2 must beset large. However, when the values of the high resistance loads R1 andR2 are set large, it becomes difficult to stably maintain the potentialat the node having the driver transistor which is OFF, that is, thepotential at the node S1 in FIG. 3.

Because of the above described background, the TFT load type SRAM whichuses the TFT as the load in place of the high resistance load has beendeveloped.

Next, a description will be given of the TFT load type SRAM. Similarlyto the description given above in respect of the high resistance loadtype SRAM, a description will first be given of the method of producingthe TFT load type SRAM.

An example of a conventional method of producing the TFT load type SRAMwill be described with reference to FIGS. 4A through 4D and FIGS. 5Athrough 5D. FIGS. 4A through 4D are side views in cross section showingessential parts of the TFT load type SRAM at essential stages of theconventional method of producing the high resistance load type SRAM.FIGS. 5A through 5D are plan views of the TFT load type SRAM atessential stages of the conventional method of producing the TFT loadtype SRAM. FIGS. 4A through 4D respectively are cross sections takenalong a line which corresponds to a line Y--Y in the plan view of FIG.5D.

The processes of producing the TFT load type SRAM at the beginning arebasically the same as the processes described in conjunction with FIGS.1A through 1G up to the process of forming the load resistor contacthole 9A of the high resistance load type SRAM, and a description thereofwill be omitted. The only difference is that a contact hole 8A shown inFIG. 5A is formed with respect to the ground line 8 which is made of thesecond polysilicon layer, so that a gate electrode of a TFT which isformed by a third polysilicon layer can make contact with an activeregion and the gate electrode 4 which is formed by the first polysiliconlayer. Hence, a description will only be given from the processesthereafter. In FIGS. 4A through 4D and 5A through 5D, those parts whichare the same as those corresponding parts in FIGS. 1A through 1J and 2Athrough 2F are designated by the same reference numerals.

In FIGS. 4A and 5A, a CVD is carried out to form a third polysiliconlayer having a thickness of 1500 Å, for example.

Then, an ion implantation is carried out to inject P ions with a dosageof 4×10¹⁵ cm⁻² and an acceleration energy of 30 keV.

Further, a resist process of the photolithography technique and a RIEusing CCl₄ /O₂ as the etching gas are carried out to pattern the thirdpolysilicon layer and form a gate electrode 15 of the TFT.

In FIG. 4B, a CVD is carried out to form a gate insulator layer 16 ofthe TFT, which is made of SiO₂ and has a thickness of 300 Å, forexample.

A resist process of the photolithography technique and a wet etchingusing hydrofluoric acid as the etchant are carried out to selectivelyetch the gate insulator layer 16 and form a drain contact hole 16A.

In FIGS. 4C and 5B, a CVD is carried out to form a fourth polysiliconlayer having a thickness of 500 Å, for example. In addition, a resistprocess of the photolithography technique and an ion implantation arecarried out to inject impurities into the fourth polysilicon layer toform a source and a drain of the TFT.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the fourth polysiliconlayer and form a source region 17, a drain region 18 and a channelregion 19 of the TFT and also form a Vcc supply line 20.

In FIGS. 4D and 5C, a CVD is carried out to form an insulator layer madeof SiO₂ and having a thickness of 1000 Å, for example, and an insulatorlayer made of PSG and having a thickness of 5000 Å, for example. In FIG.4D, these two insulator layers are shown as one insulator layer 21,similarly as in the case of FIGS. 1I and 1J.

Then, a thermal process is carried out to reflow and planarize theinsulator layer 21.

Next, a resist process of the photolithography technique and a RIE usingCHF₃ /He as the etching gas are carried out to selectively etch theinsulator layer 21 and the like and to form a bit line contact hole.

A sputtering is carried out thereafter to form an Al layer having athickness of 1 μm, for example, and this Al layer is patterned by thenormal photolithography technique to form a bit line 22. Those elementswhich are shown in FIGS. 4D and 5C but not yet described, such as "BL"will be readily understood from the description given later inconjunction with FIG. 6.

FIG. 5D shows the plan view of the essential part of the TFT load typeSRAM which is completed by the above described processes. In FIG. 5D,those parts which are the same as those corresponding parts in FIGS. 4Athrough 4D and FIGS. 5A through 5D are designated by the same referencenumerals. However, for the sake of convenience, the illustration of theAl bit line 22 shown in FIGS. 4D and 5C is omitted in FIG. 5D.

FIG. 6 shows an equivalent circuit diagram of an essential part of theTFT load type SRAM described in conjunction with FIGS. 4A through 4D and5A through 5D. In FIG. 6, those parts which are the same as thosecorresponding parts in FIGS. 4A through 4D and 5A through 5D aredesignated by the same reference numerals.

FIG. 6 shows transistors Q5 and Q6 which are load TFTs used in place ofthe high resistance loads R1 and R2 shown in FIG. 3.

Next, a description will be given of the operation of the TFT load typeSRAM, and the storing operation in particular.

If it is assumed that the positive power source voltage Vcc is 5 V, thenegative power source voltage Vss is 0 V, the node S1 is 5 V and thenode S2 is 0 V, the transistor Q6 is OFF when the transistor Q2 is ONand the transistor Q5 is ON when the transistor Q1 is OFF. The potentialat the node S1 is maintained to 5 V if the transistor Q1 is OFF and theresistance is sufficiently high compared to the transistor Q5 which isON. The potential at the node S2 is maintained to 0 V if the transistorQ2 is ON and the resistance is sufficiently small compared to thetransistor Q6 which is OFF.

Under the above described condition, the resistance of the loadtransistor Q5 or Q6 changes depending on the stored information, andthus, the problems of the high resistance load type SRAM is eliminated.That is, it is possible to carry out a stable information storageoperation. The channels of the transistors Q5 and Q6, that is, thechannels of the load TFTs, are made of polysilicon. The crystal state ofthe polysilicon which forms the channels is considerably poor comparedto the single crystal, and a current easily leaks even when thetransistor is OFF. Such a leak current increases the current consumptionof the chip, and it is desirable to make the channel as small aspossible.

On the other hand, as may be readily seen from FIG. 4D, the bit line 22which is made of the Al layer is provided at the top layer of the TFTload type SRAM. In addition, the channel of the load TFT existsimmediately under the bit line 22 via the insulator layer 21 which ismade of PSG or the like.

But according to this construction, the bit line 22 which is made of theAl layer can be regarded as a gate electrode of a transistor, and theunderlying insulator layer 21 can be regarded as a gate insulator layerof this transistor. In addition, the potential of the bit line 22 whichis regarded as the gate electrode varies between 0 v (Vss) and 5 V(Vcc). As a result, the TFT which should be OFF, that is, the transistorQ6 becomes nearly ON, and the leak current increases and the parasiticeffect becomes notable.

Accordingly, a double gate structure TFT load type SRAM was developed inorder to eliminate the above described problems of the TFT load typeSRAM.

According to the double gate structure TFT load type SRAM, the abovedescribed problems of the TFT load type SRAM are eliminated byinterposing the third polysilicon layer of the TFT load type SRAMdescribed in conjunction with FIGS. 4 through 6 between the fourthpolysilicon layer and the bit line 22 which is made of Al. Particularly,a fifth polysilicon layer forming a second gate electrode which has thesame pattern as the gate electrode 15 of the TFT is interposed betweenthe Al bit line 22 and the fourth polysilicon layer which forms thesource region 17, the drain region 18, the channel region 19, the Vccsupply line 20 and the like.

FIGS. 7A through 7C are side views in cross section showing essentialparts of the double gate structure TFT load type SRAM at essentialstages of the conventional method of producing the double gate structureTFT load type SRAM. The processes of producing the double gate structureTFT load type SRAM at the beginning are basically the same as theprocesses described in conjunction with FIGS. 4A through 4C up to theprocess of forming the source region 17, the drain region 18, thechannel region 19 and the Vcc supply line 20 of the TFT load type SRAM,and a description thereof will be omitted. Hence, a description willonly be given from the processes thereafter. In FIGS. 7A through 7C,those parts which are the same as those corresponding parts in FIGS. 1through 6 are designated by the same reference numerals.

In FIG. 7A, a CVD is carried out to form an insulator layer 23 which ismade of SiO₂ and has a thickness of 500 Å, for example.

A resist process of the photolithography technique and a RIE using CHF₃+He as the etching gas are carried out to selectively etch the insulatorlayer 23 and to form a contact hole 23A with respect to the drainelectrode 18 of the TFT.

In FIG. 7B, a CVD is carried out to form a fifth polysilicon layerhaving a thickness of 1000 Å, for example.

Then, an ion implantation is carried out to inject P ions into the fifthpolysilicon layer with a dosage of 4×10¹⁵ cm⁻² for example

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the fifth polysiliconlayer and to form a second gate electrode 24 of the TFT.

In FIG. 7C, a CVD is carried out to form an insulator layer which ismade of SiO₂ and has a thickness of 1000 Å, for example, and aninsulator layer which is made of PSG and has a thickness of 5000 Å, forexample. As in the case shown in FIG. 4D, these two insulator layers areshown as one insulator layer 25 in FIG. 7C.

Thereafter, a thermal process is carried out to reflow and planarize theinsulator layer 25.

Next, a resist process of the photolithography technique and a RIE usingCHF₃ /He as the etching gas are carried out to selectively etch theinsulator layer 25 and the like, and to form a bit line contact hole.

In addition, a sputtering is carried out to form an Al layer having athickness of 1 μm, for example, and this Al layer is patterned by thenormal photolithography technique so as to form a bit line 26.

As described heretofore, the SRAM started from the high resistance loadtype, evolved to the TFT load type, and further evolved to the doublegate structure TFT load type. However, as may be seen by comparing FIGS.1A through 1J with FIGS. 7A through 7C, and FIGS. 1J and 7C inparticular, the number of polysilicon layers has increased by two fromthe high resistance load type SRAM to the double gate structure TFT loadtype SRAM, and the number of mask processes have increased by four.

Therefore, the parasitic effect is generated in the case of the TFT loadtype SRAM, and there are problems in that the bit line voltage or thelike causes the TFT load which should be OFF to assume a state near theON state and the leak current increases, as described above. Butalthough the double gate structure TFT load type SRAM was developed tosuppress the problems of the TFT load type SRAM, problems are introducedfrom the production point of view in that the number of mask processesincreases, as described above.

SUMMARY OF THE INVENTION

Accordingly, it is a general object of the present invention to providea novel and useful thin film transistor (TFT) load type static randomaccess memory (SRAM) in which the problems described above areeliminated.

Another and more specific object of the present invention is to providea semiconductor memory device comprising a semiconductor substrate, anda memory cell formed on the semiconductor substrate and including twotransfer transistors, two driver transistors and two thin filmtransistor loads, where the thin film transistor load includes a firstgate electrode, a first insulator layer formed on the first gateelectrode, a semiconductor layer formed on the first insulator layer, asecond insulator layer formed on the semiconductor layer, and a shieldelectrode formed on the second insulator layer, and the shield electrodeshields the thin film transistor. According to the semiconductor memorydevice of the present invention, the thin film transistor load iscovered by the shield electrode, and it is possible to prevent unstableoperation caused by the potential at a conductive part within the memorycell.

Still another object of the present invention is to provide a method ofproducing a semiconductor memory device which includes a memory cellhaving two transfer transistors, two driver transistors and two thinfilm transistor loads, comprising the steps of (a) forming a gateinsulator layer after forming a field insulator layer on a surface of asemiconductor substrate, (b) forming a first conductor layer on thesemiconductor substrate and patterning the first conductor layer to forma gate electrode of the driver transistor, (c) forming a first insulatorlayer after forming impurity regions in the semiconductor substrate byintroducing impurities into the semiconductor substrate using the fieldinsulator layer and the gate electrode of the driver transistor asmasks, (d) forming a second conductor layer and patterning the secondconductor layer to form a gate electrode of the thin film transistorload, (e) forming a second insulator layer which forms a gate insulatorlayer, (f) forming a third conductor layer which is made of asemiconductor and forming source, drain and channel regions of the thinfilm transistor load in the third conductor layer by selectivelyintroducing impurities into the third conductor layer and patterning thethird conductor layer, (g) forming a third insulator layer which coversthe third conductor layer, and (h) forming a fourth conductor layer onthe third insulator layer and patterning the fourth conductor layer toform a shield electrode of the thin film transistor load. According tothe method of the present invention, it is possible to produce thesemiconductor memory device using a small number of mask processes.

Other objects and further features of the present invention will beapparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A through 1J are side views in cross section showing essentialparts of a high resistance load type SRAM at essential stages of aconventional method of producing the high resistance load type SRAM;

FIGS. 2A through 2F are plan views of the high resistance load type SRAMat essential stages of the conventional method of producing the highresistance load type SRAM;

FIG. 3 shows an equivalent circuit diagram of the essential part of thehigh resistance load type SRAM described in conjunction with FIGS. 1Athrough 1J and 2A through 2F;

FIGS. 4A through 4D are side views in cross section showing essentialparts of a TFT load type SRAM at essential stages of a conventionalmethod of producing the high resistance load type SRAM;

FIGS. 5A through 5D are plan views of the TFT load type SRAM atessential stages of the conventional method of producing the TFT loadtype SRAM;

FIG. 6 shows an equivalent circuit diagram of an essential part of theTFT load type SRAM described in conjunction with FIGS. 4A through 4D and5A through 5D;

FIGS. 7A through 7C are side views in cross section showing essentialparts of a double gate structure TFT load type SRAM at essential stagesof a conventional method of producing the double gate structure TFT loadtype SRAM;

FIGS. 8A and 8B are side views in cross section showing an essentialpart of a first embodiment of a semiconductor memory device according tothe present invention at essential stages of a first embodiment of amethod of producing the semiconductor memory device according to thepresent invention;

FIG. 9 is a plan view showing an essential part of the first embodimentof the semiconductor memory device at an essential stage of the firstembodiment of the method of producing the semiconductor memory deviceaccording to the present invention;

FIGS. 10A through 10C are side views in cross section showing anessential part of a second embodiment of a semiconductor memory deviceaccording to the present invention at essential stages of a secondembodiment of a method of producing the semiconductor memory deviceaccording to the present invention;

FIG. 11 is a plan view showing an essential part of a TFT load type SRAMto which the present invention may be applied;

FIGS. 12A through 12I are side views in cross section showing anessential part of a third embodiment of a semiconductor memory deviceaccording to the present invention at essential stages of a thirdembodiment of a method of producing the semiconductor memory deviceaccording to the present invention;

FIGS. 13A through 13F are side views in cross section showing essentialparts of a semiconductor memory device at essential stages of theproduction, for explaining the process of forming a contact hole whichpenetrates a stacked structure;

FIGS. 14A through 14F are side views in cross section showing anessential part of a fourth embodiment of the semiconductor memory deviceaccording to the present invention at essential stages of a fourthembodiment of the method of producing the semiconductor memory deviceaccording to the present invention, for explaining the operatingprinciple of the fourth embodiment;

FIGS. 15A through 15H are side views in cross section showing anessential part of the fourth embodiment of the semiconductor memorydevice according to the present invention at essential stages of thefourth embodiment of the method of producing the semiconductor memorydevice according to the present invention; and

FIGS. 16A through 16D are side views in cross section showing anessential part of a fifth embodiment of the semiconductor memory deviceaccording to the present invention at essential stages of a fifthembodiment of the method of producing the semiconductor memory deviceaccording to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First, a description will be given of a first embodiment of asemiconductor memory device according to the present invention which isproduced by a first embodiment of a method of producing thesemiconductor memory device according to the present invention. FIGS. 8Aand 8B are side views in cross section showing an essential part of thefirst embodiment of the semiconductor memory device according to thepresent invention at essential stages of the first embodiment of themethod of producing the semiconductor memory device according to thepresent invention. In FIGS. 8A and 8B, those parts which are the same asthose corresponding parts in FIGS. 4A through 4D are designated by thesame reference numerals.

FIG. 9 shows an essential part of the first embodiment in a plan view.FIG. 9 differs from the prior art FIG. 5D in that a shield electrode 30is additionally provided. FIGS. 8A and 8B respectively are crosssections taken along a line which corresponds to a line Y--Y in the planview of FIG. 9.

In this embodiment of the method, the processes are the same as those ofthe prior art up to the processes shown in FIGS. 4A through 4C, that is,until a fourth polysilicon layer is used to form a source region 17, adrain region 18 and a channel region 19 of the TFT load and a Vcc supplyline 20. Hence, a description will only be given of the processescarried out thereafter.

In FIGS. 8A and 9, the TFT load type SRAM already has provided on a Sisemiconductor substrate 1 a field insulator layer 2, a gate insulatorlayer 3, a gate electrode of the transfer transistor or a gate electrode4 of the driver transistor formed from a first polysilicon layer, an n⁺-type impurity region 5', an n⁺ -type source region 5, an n⁺ -type drainregion 6, a SiO₂ insulator layer 7, a ground line 8 formed from a secondpolysilicon layer, a SiO₂ insulator layer 9, a gate electrode 15 of theTFT load formed from a third polysilicon layer, a gate insulator layer16 of the TFT load made of SiO₂, and the source region 17, the drainregion 18 and the channel region of the TFT load and the Vcc supply line(not shown) which are formed from the fourth polysilicon layer.

A CVD is carried out to form on the entire surface an insulator layer 29which is made of SiO₂ and has a thickness of 500 Å, for example.

Then, a CVD is carried out to form on the entire surface a fifthpolysilicon layer having a thickness of 1000 Å, for example.

A thermal diffusion process is carried out to diffuse P in the fifthpolysilicon layer with an impurity concentration of 1×10²¹ cm⁻³, forexample.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the fifth polysiliconlayer and to form the shield electrode 30.

In FIGS. 8B and 9, a CVD is carried out to form an insulator layer whichis made of SiO₂ and has a thickness of 1000 Å, for example, and aninsulator layer which is made of PSG and has a thickness of 5000 Å, forexample. In FIG. 8B, these two insulator layers are shown as aninsulator layer 31, similarly as in the case of FIG. 4D.

Thereafter, a thermal process is carried out to reflow and planarize theinsulator layer 31.

A resist process of the photolithography technique and a RIE using CHF₃/He as the etching gas are carried out to selectively etch the insulatorlayer 31 and the like and to form a bit line contact hole.

Then, a sputtering is carried out to form an Al layer having a thicknessof 1 μm, for example, and this Al layer is patterned into a bit line 32using the normal photolithography technique.

According to this embodiment, the TFT load is shielded by the shieldelectrode 30. For this reason, it is possible to prevent undesirable anderroneous operation which may be caused by the voltage of the bit line32 or other conductive parts. In addition, the number of mask processesis reduced by one compared to that of the double gate structure TFT loadtype SRAM, and the production process can thus be simplified.

Next, a description will be given of a second embodiment of thesemiconductor memory device according to the present invention which isproduced by a second embodiment of the method of producing thesemiconductor memory device according to the present invention. FIGS.10A through 10C are side views in cross section showing an essentialpart of the second embodiment of the semiconductor memory deviceaccording to the present invention at essential stages of the secondembodiment of the method of producing the semiconductor memory deviceaccording to the present invention. In FIGS. 10A through 10C, thoseparts which are the same as those corresponding parts in FIGS. 4Athrough 4D are designated by the same reference numerals. FIGS. 10Athrough 10C respectively are cross sections taken along a line which issimilar to the line Y--Y in the plan view of FIG. 9.

In this embodiment of the method, the processes are the same as those ofthe prior art up to the processes shown in FIGS. 4A and 4B, that is,until a gate insulator layer 16 is selectively etched to form a draincontact hole 16A. Hence, a description will only be given of theprocesses carried out thereafter.

In FIG. 10A, the TFT load type SRAM already has provided on a Sisemiconductor substrate 1 a field insulator layer 2, a gate insulatorlayer 3, a gate electrode 4 of the driver transistor formed from a firstpolysilicon layer, an n⁺ -type impurity region 5', an n⁺ -type sourceregion 5, an n⁺ -type drain region 6, a SiO₂ insulator layer 7, a groundline 8 formed from a second polysilicon layer, a SiO₂ insulator layer 9,a gate electrode 15 of the TFT load formed from a third polysiliconlayer, the gate insulator layer 16 of the TFT load made of SiO₂, and thedrain contact hole 16A. The drain contact hole 16A is shown in FIG. 4B.

A CVD is carried out to form a fourth polysilicon layer having athickness of 200 Å, for example.

Then, a resist process of the photolithography technique and an ionimplantation are carried out to inject B ions with a dosage of 1×10¹⁴cm⁻² and an acceleration energy of 5 keV, for example, into parts of thefourth polysilicon layer where source and drain regions of the TFT loadare formed.

In FIG. 10B, a CVD is carried out to form on the entire surface aninsulator layer 29 which is made of SiO₂ and has a thickness of 500 Å,for example.

A CVD is carried out to form on the entire surface a fifth polysiliconlayer having a thickness of 1000 Å, for example.

Next, a thermal diffusion process is carried out to diffuse P in thefifth polysilicon layer with an impurity concentration of 1×10²¹ cm⁻³,for example.

A resist process of the photolithography technique and RIEs using CCl₄/O₂ and CHF₃ /He as the etching gases are carried out to pattern thefifth polysilicon layer, the insulator layer 29 and the fourthpolysilicon layer and to form a shield electrode 30, a source region 17,a drain region 18 and a channel region 19 of the TFT load, and a Vccsupply line. The Vcc supply line cannot be seen in FIG. 10B. The CCl₄/O₂ etching gas is used to etch the polysilicon, and the CHF₃ /He isused to etch the SiO₂.

In FIG. 10C, a CVD is carried out to form an insulator layer which ismade of SiO₂ and has a thickness of 1000 Å, for example, and aninsulator layer which is made of PSG and has a thickness of 5000 Å, forexample. These two insulator layers are shown as an insulator layer 31in FIG. 10C, similarly as in the case of FIG. 4D.

Then, a thermal process is carried out to reflow and planarize theinsulator layer 31.

A resist process of the photolithography technique and a RIE using CHF₃/He as the etching gas are carried out to selectively etch the insulatorlayer 31 and the like and to form a bit line contact hole.

A sputtering is carried out to form an Al layer having a thickness of 1μm, for example, and this Al layer is patterned into a bit line 32 bythe normal photolithography technique.

According to this embodiment, the shield electrode 30 which shields theTFT load, the source region 17, the drain region 18 and the channelregion 19 of the TFT load and the like can be formed by one maskprocess. For example, the channel of the TFT load and the shieldelectrode 30 have the same pattern (or shape) in the plan view. As aresult, although the shield electrode 30 is additionally provided, thenumber of processes will not increase when compared to the prior artdescribed with reference to FIG. 5D, for example, and the parasiticeffect of the TFT load can be prevented. In addition, when compared tothe conventional double gate structure TFT load type SRAM described withreference to FIG. 7C, for example, the number of mask processes isreduced by two.

FIG. 11 shows a plan view of an essential part of a TFT load type SRAMhaving split word lines, to which the present invention may be applied.The TFT load type SRAM shown in FIG. 11 includes a gate 41 of the TFTload, a channel 42 of the TFT load, a word line 43 (WL), and a Vccsupply line for supplying a positive power source voltage Vcc.

This TFT load type SRAM shown in FIG. 11 has the driver transistors andthe TFT loads arranged with a symmetrical layout. Accordingly, there isan advantage in that the layout design is easy to make.

A description will now be given of an embodiment in which the presentinvention is applied to the TFT load type SRAM shown in FIG. 11.

FIGS. 12A through 12I are side views in cross section showing anessential part of a third embodiment of the semiconductor memory deviceaccording to the present invention at essential stages of a thirdembodiment of the method of producing the semiconductor memory deviceaccording to the present invention. FIGS. 12A through 12I respectivelyare cross sections taken along a line which corresponds to a line X--Xin the plan view of FIG. 11.

In FIG. 12A, a pad layer made of SiO₂ covers an active region of a Sisemiconductor substrate 51, and an oxidation resistant mask layer madeof Si₃ N₄ is formed on the pad layer. The pad layer and the oxidationresistant mask layer are used to selectively oxidize the Sisemiconductor substrate 51 by a selective thermal oxidation and to forma field insulator layer 52. This field insulator layer 52 is made ofSiO₂ and has a thickness of 4000 Å, for example.

Then, the active region is exposed by removing the oxidation resistantmask layer and the pad layer, and a thermal oxidation is carried out toform a gate insulator layer 53 which is made of SiO₂ and has a thicknessof 100 Å, for example.

A resist process of the photolithography technique and a wet etchingusing hydrofluoric acid as the etchant are carried out to selectivelyetch the gate insulator layer 53 and to form a contact hole which isalso used for diffusing impurities.

A CVD is carried out to form a first polysilicon layer having athickness of 1000 Å, for example.

Next, a vapor phase diffusion is carried out to introduce P into thefirst polysilicon layer with an impurity concentration of 1×10²⁰ cm⁻³,for example, and to form an n⁺ -type impurity region 54.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the first polysiliconlayer and to form gate electrodes 55 and 56.

An ion implantation is carried out to inject As ions into the Sisemiconductor substrate 51 with a dosage of 1×10¹⁵ cm⁻² and anacceleration energy of 30 keV, for example, so as to form an n⁺ -typesource region 57 and an n⁺ -type drain region 58.

In FIG. 12B, a CVD is carried out to form an insulator layer 59 which ismade of SiO₂ and has a thickness of 1000 Å, for example.

Then, a CVD is carried out to form a second polysilicon layer having athickness of 1000 Å, for example.

A vapor phase diffusion is carried out to introduce P into the secondpolysilicon layer with an impurity concentration of 1×10²⁰ cm⁻³, forexample.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the second polysiliconlayer and to form a gate electrode 61 of the TFT load and the like.

In FIG. 12C, a CVD is carried out to form a gate insulator layer 62 ofthe TFT load, which is made of SiO₂ and has a thickness of 200 Å, forexample.

A resist process of the photolithography technique and RIEs using CHF₃/He and CCl₄ /O₂ as the etching gases are carried out to selectivelyetch the insulator layer 62, the gate electrode 61 of the TFT loadformed from the second polysilicon layer, and the insulator layer 59,and to form a contact hole 62A. This contact hole 62A extends from a topsurface of the insulator layer 62 and reaches a top surface of the gateelectrode 56 or 55 of the driver transistor formed from the firstpolysilicon layer. The CHF₃ /He etching gas is used to etch the SiO₂,and the CCl₄ /O₂ etching gas is used to etch the polysilicon.

In FIG. 12D, a CVD is carried out to form a third polysilicon layerhaving a thickness of 500 Å, for example.

Then, a resist process of the photolithography technique and an ionimplantation are carried out to inject B ions with a dosage of 1×10¹⁴cm⁻² and an acceleration energy of 5 keV, for example, into parts of thethird polysilicon layer where source and drain regions of the TFT loadand a Vcc supply line are formed.

In FIG. 12E, a CVD is carried out to form an insulator layer 65 which ismade of SiO₂ and has a thickness of 500 Å, for example.

Then, a CVD is carried out to form a fourth polysilicon layer having athickness of 1000 Å, for example.

A thermal diffusion process is carried out to diffuse P in the fourthpolysilicon layer with an impurity concentration of 1×10²⁰ cm⁻³, forexample.

In FIG. 12F, a resist process of the photolithography technique and RIEsusing CCl₄ /O₂ and CHF₃ /He as the etching gases are carried out topattern the fourth polysilicon layer, the insulator layer 65 and thethird polysilicon layer, and to form a shield electrode 66 of the TFTload, a contact part, drain, source and channel regions of each TFTload, a Vcc supply line and the like. The CCl₄ /O₂ etching gas is usedto etch the polysilicon, and the CHF₃ /He etching gas is used to etchthe SiO₂.

Not all of the parts described above, and the TFT load formed from thethird polysilicon layer in particular, cannot be seen in FIG. 12Fbecause these parts extend in a direction perpendicular to the paper inFIG. 12F. For this reason, only a contact part 63 which connects to atip end of a drain region of a certain TFT load and a channel region 64of a TFT load which is adjacent to this certain. TFT load are shown inFIG. 12F. The contact part 63 which is formed from the third polysiliconlayer makes contact with the top surface of the gate electrode 56 of thedriver transistor and with the side surface of the gate electrode 61 ofthe TFT load, within the contact hole 62A. In addition, the shield ofthe TFT load sufficiently functions as the shield if the shieldelectrode 66 mainly covers the channel surface region of the TFT load.

In FIG. 12G, a CVD is carried out to form an insulator layer 67 which ismade of SiO₂ and has a thickness of 1000 Å, for example.

Then, a resist process of the photolithography technique and a RIE usingCHF₃ /He as the etching gas are carried out to selectively etch theinsulator layer 67 and the like and to form a contact hole 67A for theVss supply (ground) line.

In FIG. 12H, a CVD is carried out to form a fifth polysilicon layerhaving a thickness of 1000 Å, for example.

Thereafter, a thermal diffusion process is carried out to diffuse P inthe fifth polysilicon layer with an impurity concentration of 1×10²¹cm⁻³, for example.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the fifth polysiliconlayer and to form a Vss supply (ground) line 68 for supplying a powersource voltage Vss.

In FIG. 12I, a CVD is carried out to form an insulator layer 69 which ismade of PSG and has a thickness of 5000 Å, for example.

Next, a thermal process is carried out to reflow and planarize theinsulator layer 69.

A resist process of the photolithography technique and a RIE using CCl₄as the etching gas are carried out to selectively etch the insulatorlayer 69 and the like and to form a bit line contact hole. This bit linecontact hole cannot be seen in FIG. 12I, but may be seen in FIG. 11, forexample.

A sputtering is carried out to form an Al layer having a thickness of 1μm, for example, and this Al layer is patterned into a bit line 70 bythe normal photolithography technique.

According to this embodiment, the TFT load is shielded by the shieldelectrode 66 and the TFT load type SRAM having the split word lines isunaffected by noise. In the case of the TFT load type SRAM having thesplit word lines, the ground line is provided above the TFT load, andthe elimination of noise is very important because the potential at theground line turns the TFT load ON and the interlayer insulator isrelatively thin. Therefore, this noise elimination feature of thisembodiment is extremely useful.

In addition, the advantageous features of the TFT load type SRAM shownin FIG. 11 is inherited in this embodiment. Furthermore, since the drainregion and the gate electrode of the TFT load and the gate electrode orthe drain region of the driver transistor can be connected by a singlemask process, the number of mask processes is reduced by one compared tothat of the second embodiment. When compared to the conventional doublegate structure TFT load type SRAM, the number of mask processes isreduced by three, and the production process is considerably simplified.

In the embodiments described above, the insulator layers made of SiO₂and the polysilicon layers are etched during the process of forming thecontact holes, such as the contact hole 9A (not shown in FIG. 8A butshown in FIG. 1G) and the contact hole 62A shown in FIG. 12C. However,the following problems may occur when penetrating the stacked structurewhich is made up of the insulator layers and polysilicon layers.

FIGS. 13A through 13F are side views in cross section showing essentialparts of a semiconductor memory device at essential stages of theproduction, for explaining the process of forming a contact hole whichpenetrates a stacked structure. In each of FIGS. 13A through 13F, theleft hand side shows the result of an expected process while the righthand side shows the result of an actual process, and the descriptionwill be given mainly with reference to the right hand side of FIGS. 13Athrough 13F which shows the actual process.

In FIG. 13A, a first conductor layer 932 made of polysilicon, a firstinsulator layer 933 made of SiO₂, a second conductor layer 934 made ofpolysilicon, a second insulator layer 935 made of SiO₂, a thirdconductor layer 936 made of polysilicon and a third insulator layer 937made of SiO₂ are successively formed and stacked on a Si semiconductorsubstrate 931.

In FIG. 13B, a resist process of the normal photolithography techniqueand a RIE using CHF₃ /He as the etching gas are carried out to etch thethird insulator layer 937 and to form a part of a contact hole. In FIG.13B, the illustration of a photoresist layer is omitted for the sake ofconvenience. The illustration of the photoresist layer will be omittedsimilarly in FIGS. 13C through 13F which follow.

When etching the third insulator layer 937, a part of the underlyingthird conductor layer 936 is also etched. As a result, the remainingthird conductor layer 936 becomes extremely thin when the thirdconductor layer 936 is thin to start with.

In FIG. 13C, a RIE using CCl₄ /O₂ as the etching gas is carried out toetch the third conductor layer 936.

Although dependent on the thickness of the underlying second insulatorlayer 935, the thickness of the second insulator layer 935 becomesextremely thin when the third conductor layer 936 is etched. In anextreme case, not only the second insulator layer 935 but also a part ofthe second conductor layer 934 may be etched when etching the thirdconductor layer 936.

In FIG. 13D, a RIE using CHF₃ /He as the etching gas is carried out toetch the second insulator layer 935. However, although this etching isoriginally intended to etch the second insulator layer 935, the secondinsulator layer 935 may not exist from the start of this etching, forthe reasons described above.

If the second insulator layer 935 is extremely thin or does not evenexist at the start of this etching, the second conductor layer 934 andthe first insulator layer 933 are etched although this etching isoriginally intended to etch the second insulator layer 935. When thesecond conductor layer 934 and the first insulator layer 933 are etched,the surface of the first conductor layer 932 may become exposed by thisetching which is originally intended to etch the second insulator layer935.

In FIG. 13E, a RIE using CCl₄ /O₂ as the etching gas is carried out toetch the second conductor layer 934.

However, although this etching is originally intended to etch the secondconductor layer 934, the surface of the first conductor layer 932 mayalready be exposed as described above. In this case, even a part of theSi semiconductor substrate 931 may be etched by this etching which isoriginally intended to etch the second conductor layer 934.

In FIG. 13F, a RIE using CHF₃ /He as the etching gas is carried out toetch the first insulator layer 933.

But although this etching is originally intended to etch the firstinsulator layer 933, a part of the Si semiconductor substrate 931 mayalready be etched as described above. In this case, the contact holecompletely extends into the Si semiconductor substrate 931 as shown inFIG. 13F and the Si semiconductor substrate 931 is extremely damaged.

If the contact hole extends into the Si semiconductor substrate 931 asshown in FIG. 13F, a leak is introduced at a node part between thedriver transistor and the load transistor of the memory cell, and theoperation of the memory cell becomes unstable. Hence, it is conceivableto carry out a moderate etching so as to etch only the originallyintended layer, but such a moderate etching is difficult to control.

The etching of each layer cannot be controlled to etch only theoriginally intended layer by the moderate etching, because the contacthole is seldom formed at a flat part shown in FIGS. 13A through 13F. Inactual practice, the contact hole is usually formed at a stepped part,and an etching residue tends to remain at the stepped part within thecontact hole. However, a sufficient over-etching becomes necessary inorder to remove such an etching residue.

Next, a description will be given of a fourth embodiment of thesemiconductor memory device according to the present invention which isproduced by a fourth embodiment of the method of producing thesemiconductor memory device according to the present invention. FIGS.14A through 14F are side views in cross section showing an essentialpart of the fourth embodiment of the semiconductor memory deviceaccording to the present invention at essential stages of-the fourthembodiment of the method of producing the semiconductor memory deviceaccording to the present invention, for explaining the operatingprinciple of the third embodiment. In each of FIGS. 14A through 14F, theleft hand side shows the result of an expected process while the righthand side shows the result of an actual process, and the descriptionwill be given mainly with reference to the right hand side of FIGS. 14Athrough 14F which shows the actual process.

In this embodiment, measures are taken so that the contact hole will notextend into the substrate even when an over-etching is carried out toremove the etching residue within the contact hole.

In FIG. 14A, a first conductor layer 142 made of polysilicon, a secondconductor layer 143 made of a refractory metal such as W and Mo or asilicide thereof, a first insulator layer 144 made of SiO₂, a thirdconductor layer 145 made of polysilicon, a second insulator layer 146made of SiO₂, a fourth conductor layer 147 made of polysilicon and athird insulator layer 148 made of SiO₂ are successively formed andstacked on a Si semiconductor substrate 141.

In FIG. 14B, a resist process of the normal photolithography techniqueand a RIE using CHF₃ /He as the etching gas are carried out to etch thethird insulator layer 148 and to form a part of a contact hole. In FIG.14B, the illustration of a photoresist layer is omitted for the sake ofconvenience. The illustration of the photoresist layer will be omittedsimilarly in FIGS. 14C through 14F which follow.

During this process, a part of the fourth conductor layer 147 underlyingthe third insulator layer 148 is also etched. Accordingly, the thicknessof the fourth conductor layer 147 remaining after this etching is alsoextremely small, similarly as in the case described above with referenceto FIGS. 13A through 13F.

In FIG. 14C, a RIE using HBr/Ar as the etching gas is carried out toetch the fourth conductor layer 147.

In this case, although dependent on the thickness of the secondinsulator layer 146 underlying the fourth conductor layer 147, thethickness of the second insulator layer 146 would be reduced by thisetching. In an extreme case, not only the second insulator layer 146 butalso a part of the third conductor layer 145 becomes etched by thisetching which is originally intended to etch the fourth conductor layer147.

In FIG. 14D, a RIE using CHF₃ /He as the etching gas is carried out toetch the second insulator layer 146.

However, the thickness of the second insulator layer 146 is alreadyreduced to start with and may not even exist in an extreme case, asdescribed above. Hence, although this etching is originally intended toetch the second insulator layer 146, the third conductor layer 145 andthe first insulator layer 144 may be etched to expose the surface of thesecond conductor layer 143.

In FIG. 14E, a RIE using HBr/Ar as the etching gas is carried out toetch the third conductor layer 145.

Even though the surface of the second conductor layer 143 may already beexposed as described above when this etching is carried out, the secondconductor layer 143 is made of the refractory metal or refractory metalsilicide. For this reason, the second conductor layer 143 is hardlyetched by this RIE which uses HBr, and no problems will be introduced bythis RIE.

In FIG. 14F, a RIE using CHF₃ /He as the etching gas is carried out toetch the first insulator layer 144.

The first insulator layer 144 may already be etched when this etching isstarted, but no adverse effects are introduced because the secondconductor layer 143 is made of the refractory metal or refractory metalsilicide and is hardly etched by the CHF₃ /He etching gas.

Therefore, the contact hole is formed to an ideal shape. The onlydifference of the resulting contact hole shown in FIG. 14F with thatshown in FIG. 13F is that the lowermost conductor layer in FIG. 14F ismade up of the first conductor layer 142 and the second conductor layer143.

Next, a more detailed description will be given of the fourth embodimentof the semiconductor memory device according to the present inventionand the fourth embodiment of the method of producing the semiconductormemory device according to the present invention, by referring to FIGS.15A through 15H. FIGS. 15A through 15H are side views in cross sectionshowing an essential part of the fourth embodiment of the semiconductormemory device according to the present invention at essential stages ofthe fourth embodiment of the method of producing the semiconductormemory device according to the present invention. In this embodiment,the present invention is applied to the TFT load type SRAM.

In FIGS. 15A through 15H, those parts which are the same as thosecorresponding parts in FIGS. 1A through 1F and FIGS. 4A through 4D aredesignated by the same reference numerals, and a description thereofwill be omitted. In this embodiment of the method, the processes are thesame as those of the prior art method up to the processes shown in FIGS.1A through 1F, that is, until the gate insulator layer 3 is selectivelyetched to form the contact hole 3A. Hence, a description will only begiven of the processes carried out thereafter. In the followingdescription, the prior art processes descried with reference to FIGS. 4Athrough 4D will help the understanding of this embodiment.

In FIG. 15A, it is assumed that the field insulator layer 2, the gateinsulator layer 3 and the contact hole 3A are already formed on the Sisemiconductor substrate 1.

A CVD is carried out to form a first polysilicon layer having athickness of 1000 Å, for example. This first polysilicon layercorresponds to the first conductor layer.

By carrying out a vapor phase diffusion, P is introduced with animpurity concentration of 1×10²¹ cm⁻³ to form an n⁺ -type impurityregion 5'.

A CVD is carried out to form a WSi layer 150 having a thickness of 1000Å, for example. This WSi layer 150 corresponds to the second conductorlayer. The material used for the layer 150 is not limited to WSi, butother refractory metals such as W or refractory metal silicides may beused in place of WSi.

In FIG. 15B, a resist process of the photolithography technique and aRIE using CCl₄ /O₂ as the etching gas for etching WSi and polysiliconare carried out to pattern the WSi layer 150 and the first polysiliconlayer and to form a gate electrode 4. This gate electrode 4 is the gateelectrode of the driver transistor and the word line.

An ion implantation is carried out to inject As ions with a dosage of3×10¹⁵ cm⁻² and an acceleration energy of 40 keV, so as to form a sourceregion 5 and a drain region 6.

In FIG. 15C, a CVD is carried out to form an insulator layer 7 which ismade of SiO₂ and has a thickness of 1000 Å, for example.

A resist process of the photolithography technique and a RIE using CHF₃/He as the etching gas are carried out to form a ground line contacthole. This ground line contact hole cannot be shown in FIG. 15C, butthis ground line contact hole may be understood from FIG. 2B, forexample.

In FIG. 15D, a CVD is carried out to form a second polysilicon layerwhich has a thickness of 1500 Å, for example.

In addition, an ion implantation is carried out to inject P ions intothe second polysilicon layer.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the second polysiliconlayer and to form a ground line 8.

In FIG. 15E, a CVD is carried out to form an insulator layer 9 which ismade of SiO₂ and has a thickness of 1000 Å, for example, on the entiretop surface of the stacked structure shown in FIG. 15D.

A CVD is carried out to form a third polysilicon layer which has athickness of 500 Å, for example.

An ion implantation is carried out to inject P ions with a dosage of1×10¹⁵ cm⁻² and an acceleration energy of 10 keV.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the third polysiliconlayer and to form a gate electrode 15 of the TFT.

In FIG. 15F, a CVD is carried out to form a gate insulator layer 16which is made of SiO₂ and has a thickness of 200 Å, for example,

A resist process of the photolithography technique and RIEs using CHF₃/He and HBr/Ar as the etching gases for respectively etching SiO₂ andpolysilicon are carried out, to selectively etch the gate insulatorlayer 16, the gate electrode 15 which is made of the third polysiliconlayer, the insulator layer 9 and the insulator layer 7, and to form acontact hole 16A. This contact hole 16A extends from the surface of thegate insulator layer 16 and reaches the gate electrode 4 of the drivertransistor. This process forms an essential part of this embodiment.Even if a sufficient over-etching is carried out so that no etchingresidue remains within the contact hole 16A after the etching, noadverse damage is made to the surface of the underlying WSi layer 150which forms the surface of the gate electrode 4. Hence, no damage ismade to the first polysilicon layer and the surface of the Sisemiconductor substrate 1 by this over-etching.

In FIG. 15G, a CVD is carried out to form a fourth polysilicon layerhaving a thickness of 200 Å, for example.

A resist process of the photolithography technique and an ionimplantation are carried out to inject B ions with a dosage of 1×10¹⁴cm⁻² and an acceleration energy of 5 keV into parts where source anddrain regions of the TFT are formed.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the fourth polysiliconlayer and to form a source region 17, a drain region 18 and a channelregion 19 of the TFT, a Vcc supply line and the like. The Vcc supplyline cannot be shown in FIG. 15G, but the Vcc supply line may beunderstood from FIG. 2F or 5D.

In FIG. 15H, a CVD is carried out to form an insulator layer which ismade of SiO₂ and has a thickness of 1000 Å, for example, and aninsulator layer which is made of PSG and has a thickness of 5000 Å. InFIG. 15H, these two insulator layers are shown as one insulator layer 21in FIG. 15H, similarly as in the case of FIG. 4D.

Then, a thermal process is carried out to reflow and planarize theinsulator layer 21.

A resist process of the photolithography technique and a RIE using CHF₃/He as the etching gas are carried out to selectively etch the insulatorlayer 21 and to form a bit line contact hole.

A sputtering is carried out thereafter to form an Al layer having athickness of 1 μm, for example, and this Al layer is patterned using thenormal photolithography technique so as to form a bit line 22.

According to this embodiment described with reference to FIGS. 15Athrough 15H in particular, only one mask process is required to achievecontact of the gate electrode of the driver transistor, the gateelectrode of the TFT load and the drain of the TFT load. In addition,when forming the contact hole for achieving this contact, there is nopossibility of the underlayer and the substrate from becoming damagedand the characteristic of the memory cell from deteriorating even whenthe over-etching is carried out to generate no etching residue withinthe contact hole. On the other hand, in the prior art shown in FIGS. 4and 5, two mask processes are required to achieve the above describedcontact.

Next, a description will be given of a fifth embodiment of thesemiconductor memory device according to the present invention and afifth embodiment of the method of producing the semiconductor memorydevice according to the present invention, by referring to FIGS. 16Athrough 16D. FIGS. 16A through 16D are side views in cross sectionshowing an essential part of the fifth embodiment of the semiconductormemory device according to the present invention at essential stages ofthe fifth embodiment of the method of producing the semiconductor memorydevice according to the present invention. In this embodiment, thepresent invention is applied to the double gate structure TFT load typeSRAM.

In FIGS. 16A through 16D, those parts which are the same as thosecorresponding parts in FIGS. 15A through 15H are designated by the samereference numerals, and a description thereof will be omitted. In thisembodiment of the method, the processes are the same as those of thefourth embodiment of the method up to the processes shown in FIGS. 15Athrough 15E, that is, until the gate electrode 15 of the TFT is formedfrom the third polysilicon layer. Hence, a description will only begiven of the processes carried out thereafter. In the followingdescription, the prior art processes descried with reference to FIGS. 7Athrough 7C will help the understanding of this embodiment.

In FIG. 16A, a double gate structure TFT load type SRAM includes a Sisemiconductor substrate 1, a field insulator layer 2 formed on the Sisemiconductor substrate 1, a gate insulator layer 3, a gate electrode 4of the driver transistor which is made up of the first polysilicon layerand a WSi layer 150 (second conductor layer), an n⁺ -type source region5, an n⁺ -type drain region 6, an n⁺ -type diffusion region 6', aninsulator layer 7, a ground line 8 which is made up of the secondpolysilicon layer, a lower gate electrode 15 of the TFT, and a gateinsulator layer 16 of the TFT.

A CVD is carried out to form a fourth polysilicon layer which has athickness of 200 Å, for example.

A resist process of the photolithography technique and an ionimplantation are carried out to inject B ions with a dosage of 1×10¹⁴cm⁻² and an acceleration energy of 5 keV into parts where source anddrain regions of the TFT are formed.

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the fourth polysiliconlayer and to form a source region 17, a drain region 18 and a channelregion 19 of the TFT and a Vcc supply line. The Vcc supply cannot beseen in FIG. 13A.

In FIG. 16B, a CVD is carried out to form an insulator layer 23 which ismade of SiO₂ and has a thickness of 500 Å, for example.

A resist process of the photolithography technique and RIEs using CHF₃/He and HBr/Ar as the etching gases for respectively etching SiO₂ andpolysilicon are carried out to selectively etch the insulator layer 23,the drain region 18 of the TFT formed from the fourth polysilicon layer,the gate insulator layer 16, the gate electrode 15 which is formed fromthe third polysilicon layer, the insulator layer 9 and the insulatorlayer 7, and to form a contact hole 23A. This contact hole 23A extendsfrom the surface of the insulator layer 23 and reaches the gateelectrode 4 of the driver transistor. The gate electrode 4 is made up ofthe WSi layer 150 and the first polysilicon layer. This process forms anessential part of this embodiment.

In FIG. 16C, a CVD is carried out to form a fifth polysilicon layerwhich has a thickness of 500 Å, for example.

Then, a thermal diffusion is carried out to diffuse P into the fifthpolysilicon layer with an impurity concentration of 1×10²¹ cm⁻³ forexample

A resist process of the photolithography technique and a RIE using CCl₄/O₂ as the etching gas are carried out to pattern the fifth polysiliconlayer and to form an upper gate electrode 24 of the TFT.

In FIG. 16D, a CVD is carried out to form an insulator layer which ismade of SiO₂ and has a thickness of 1000 Å, for example, and aninsulator layer which is made of PSG and has a thickness of 5000 Å, forexample. In FIG. 16D, these two insulator layers are shown as oneinsulator layer 25.

Thereafter, a thermal process is carried out to reflow and planarize theinsulator layer 25.

A resist process of the photolithography technique and a RIE using CHF₃/He as the etching gas are carried out to selectively etch the insulatorlayer 25 and the like and to form a bit line contact hole.

Next, a sputtering is carried out to form an Al layer having a thicknessof 1 μm, for example, and this Al layer is patterned using the normalphotolithography technique so as to form a bit line 26.

In this embodiment, the concept shown in FIGS. 14A through 14F isapplied to the double gate structure TFT load type SRAM. When formingthe contact hole for achieving the necessary contact, there is nopossibility of the underlayer and the substrate from becoming damagedand the characteristic of the memory cell from deteriorating even whenthe over-etching is carried out to generate no etching residue withinthe contact hole. Compared to the prior art method described withreference to FIGS. 7A through 7C, the number of mask processes which arerequired to achieve the above described contact in this embodiment isreduced by two.

From the fourth and fifth embodiments described above, it is apparent tothose skilled in the art that the concept of the fourth embodiment maybe applied to each of the first through third embodiments describedabove. In other words, the ideal shape of the contact hole can beguaranteed by providing the conductor layer which is made of therefractory metal or refractory metal silicide.

Further, the present invention is not limited to these embodiments, butvarious variations and modifications may be made without departing fromthe scope of the present invention.

What is claimed is:
 1. A semiconductor memory device comprising:asemiconductor substrate; and a memory cell formed on the semiconductorsubstrate and including two transfer transistors, two driver transistorsand two thin film transistor loads, said thin film transistor loadsincluding a first gate electrode, a first insulator layer formed on thefirst gate electrode, a semiconductor layer formed on the firstinsulator layer, a second insulator layer thicker than said firstinsulator layer formed on the semiconductor layer, and a shieldelectrode formed on the second insulator layer, said shield electrodeshielding the thin film transistor loads and being out of directelectrical connection with said first gate electrode and saidsemiconductor substrate, wherein the thin film transistor loads furtherinclude a channel region formed in the semiconductor layer, and theshield electrode has a pattern identical to that of the semiconductorlayer where the channel region is formed.
 2. The semiconductor memorydevice as claimed in claim 1, wherein the shield electrode receives apositive power source voltage which corresponds to one of data values tobe stored in the memory cell.
 3. The semiconductor memory device asclaimed in claim 1, wherein the driver transistors include a second gateelectrode formed on the semiconductor substrate, a third insulator layerformed on the second gate electrode, and a contact hole which extendsfrom a top surface of the third insulator layer and reaches a topsurface of the second gate electrode, said first gate electrode of thethin film transistor loads making contact with the top surface of thesecond gate electrode within the contact hole, said shield electrodebeing out of direct electrical connection with said second gateelectrode.
 4. The semiconductor memory device as claimed in claim 3,wherein the thin film transistor loads further include a hole formed inthe first insulator layer above the contact hole, and the semiconductorlayer makes contact with the first gate electrode via the hole in thefirst insulator layer.
 5. The semiconductor memory device as claimed inclaim 3, wherein the second gate electrode of the driver transistorsincludes a first conductor layer formed on the semiconductor substrate,and a second conductor layer formed on the first conductor layer andhaving the top surface exposed within the contact hole, said secondconductor layer being made of a material selected from a groupconsisting of refractory metals and refractory metal silicides.
 6. Asemiconductor memory device as set forth in claim 1 wherein said shieldelectrode shields said driver transistors.
 7. A semiconductor memorydevice comprising:a semiconductor substrate; and a memory cell formed onthe semiconductor substrate and including two transfer transistors, twodriver transistors and two thin film transistor loads, said thin filmtransistor loads including a first gate electrode, a first insulatorlayer formed on the first gate electrode, a semiconductor layer formedon the first insulator layer, a second insulator layer thicker than saidfirst insulator layer formed on the semiconductor layer, and a shieldelectrode formed on the second insulator layer, said shield electrodeshielding the thin film transistor loads and being out of directelectrical connection with said first gate electrode and saidsemiconductor substrate, wherein the driver transistors include a secondgate electrode formed on the semiconductor substrate, and a thirdinsulator layer formed on the second gate electrode, and the thin filmtransistor loads further include a contact hole which extends from a topsurface of the first insulator layer and reaches a top surface of thesecond gate electrode, said semiconductor layer of the thin filmtransistor loads making contact with the top surface of the second gateelectrode and with a side surface of the first gate electrode within thecontact hole, said shield electrode being out of direct electricalconnection with said second gate electrode.
 8. The semiconductor memorydevice as claimed in claim 7, wherein the thin film transistor loadincludes a channel region formed in the semiconductor layer, and theshield electrode has a pattern identical to that of the semiconductorlayer which forms the channel region.
 9. The semiconductor memory deviceas claimed in claim 7, which further comprises:a fourth insulator layerformed on the shield electrode; and a ground line formed on the fourthinsulator layer above the shield electrode.
 10. The semiconductor memorydevice as claimed in claim 7, wherein the second gate electrode of thedriver transistor includes a first conductor layer formed on thesemiconductor substrate, and a second conductor layer formed on thefirst conductor layer and having the top surface exposed within thecontact hole, said second conductor layer being made of a materialselected from a group consisting of refractory metals and refractorymetal silicides.